Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure (routing resources). The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
To implement a circuit design using an FPGA, the design is mapped onto programmable logic blocks, placed within the FPGA, and routed using the programmable fabric. The place and route phases of implementing a circuit design involve generating a layout of the circuit elements on the FPGA and defining the signal lines (routing resources) that connect the elements. Performance and frequency requirements translate to a maximum allowable delay for paths traversing routing resources between circuit elements. For example, FPGAs are operating at ever-increasing frequencies. As such, designers are now concerned about pico-second-accuracy in clock frequency and skew. In addition, as device size increases, the variation of delay values across the device also increases. Thus, designers are beginning to think in terms of minimum-delay and maximum-delay during circuit design.
With conventional timing analysis, after a circuit design is mapped, placed, and routed, signal path delay is determined based on assigned costs to the physical resources of an FPGA (“resource costs”). The resource costs are based on the type of routing resource and are standard across many types of devices. For particular circuit elements, such as a local clock net, this approach has severe limitations. First, using generic resource costs, the minimum-delay value for a path will be a fraction of the maximum-delay value for the path. The fraction is determined based on an analysis of a large number of paths across many FPGAs. Thus, the minimum-delay value is typically a worst-case number. Second, the worst-case minimum-delay value results in a conservative clock skew calculation. As such, a circuit design may not exhibit optimal performance.
Accordingly, there exists a need in the art for timing characterization of an integrated circuit design that overcomes the disadvantages associated with the use of generic resource cost values during timing analysis.